This course examines the facilities available with the IBM zSeries architecture at the hardware implementation level. The following topics are covered:
Discusses the function and operation of hardware components at the host machine level. Entities described are memory systems, processor subsystems and microcode operation.
Shows the operation of the different addressing modes and the implementation of the address translation mechanisms.
Describes the facilities of the architecture at the register and data representation level. Discusses the realisation of Cross Memory Services and Data Spaces.
Describes the Dynamic Channel Subsystem and the associated interface architectures. at the channel programming and device level.
Discusses the physical storage hierarchy with special emphasis on the available facilities of external storage devices. Describes the operation of the major control units and I/O devices used in a typical system configuration.
METHODOLOGY AND PLATFORM
The course is lecture based.
At the completion of the course the learner will be able to:
- Identify and understand the operation of the primary components that are incorporated in a typical general purpose mainframe computer.
- List the functions of the system components that comprise the IBM zSeries architecture.
- Understand the principles of operation of the system components in an IBM zSeries environment.
Assessment processes are built into the course for learners as part of our commitment to life-long learning. Formative assessment is carried out during the training via Course Activities. Summative assessment commences after the training in the form of a written knowledge questionnaire and if applicable, the practical assignment that the learners are required to complete as part of their course content. Learners will receive a certificate of competence on successful completion of the course
The following material is supplied:
- A full set of notes covering the course outline.